The use of a cache for performance improvements on large and small computer systems is well known. In such systems, the principal factors determining the cache efficiency are the mapping method, cache size and line size, etc. The relationship between these factors and the efficiency is described in various papers, e. g., IEEE Transaction on Computer, "Line(Block) Choice for CPU Cache Memories", by Alan Jay Smith, September 1987, pp 1063-1075; and IEEE Computer, "Cache Based Computer System," by R. R. Kaplan, et al., March 1973, pp 30-33.
Among the principal factors, the line size has an important effect on the miss ratio of a cache. Increasing the line size decreases the miss ratio of a cache; and the miss ratio reaches its minimum at the optimum line size. That is, increasing the line size beyond the optimum value again increases the miss ratio.
Even at the optimum line size, the cache efficiency is further affected by the data transfer width between the SRAM chips employed in the cache and the DRAM chips constituting the main memory. That is, should the data transfer width be too small, the time to load the cache with a data block taken from the main memory will be longer, thereby lowering the cache efficiency.
In large computing systems, various techniques known in the art may be used to enlarge the data transfer width. However, in a small system wherein cache is a separate physical entity made of only a few high speed array chips, the bus width between the cache and the main memory is severely limited by the small signal pin count available on the cache chips.
In order to overcome this problem in small systems, U.S. Pat. No 4,577,293 issued to Richard E. Matick, et al. discloses a distributed, on-chip cache which has a large band width between the main memory array and an on-chip row buffer to provide a fast reload time on a cache miss wherein the distributed cache is achieved by the use of a communicating random access memory chip of the type incorporating a primary port and a secondary port.
The communicating random access memory chip is described in U.S. Pat. No. 4,649,516 issued to Paul W. Chung, et al.
The use of another memory device is disclosed in Symphosium on VLSI Circuit Digest of Technical Papers, "AN EXPERIMENTAL IMb CACHE DRAM WITH ECC", by Mikio Asakuro et al. pp 43-44 (May, 1989). This memory device comprises SRAM and DRAM integrated on a chip, wherein the SRAM and DRAM share internal data bus but have separate corresponding peripheral circuits.